The mcp2510 is a can protocol controller from Microchip, fully supporting the CAN bus v2.0a/b specification, capable of transmitting and receiving standard and extended messages. It also has acceptance filtering and message management capabilities. The device contains three transmit buffers and two receive buffers, reducing the management burden on the microcontroller. The communication of the single chip microcomputer is realized by the industry standard serial peripheral interface spi, and its data transmission rate is up to 5mbps. The programmable bit transfer rate on the can bus is up to 1mbps. In the PC, each parallel port occupies 3 i/o port addresses, which correspond to their respective data registers, control registers and status registers. The data register address is 378h, which is used to temporarily store the transmitted data. In the two-way communication environment, it contains double buffer registers for reading and reading two registers, corresponding to ad0 to ad7 bidirectional data/address ports, and input registers for input operations. The output register is used for output operation; the status port register address is 379h, which provides the current status of the line and external devices; the control port register address is 37ah, which provides timing control signals for transmitting data.
Circuit principle: the three-state output latch 74hc373 is used as the interface between the PC epp parallel port and the mcp2510, and the parallel port control signal is used to control the latch enable signal le and the output enable signal oe to realize computer parallel data and Data exchange between the spi bus in mcp2510. The key problem is to generate the corresponding read/write cycle timing by the system calling the microprogram in the epp chip on the motherboard in the nwrite, naddstb, ndatastb, nreset pins of the parallel port, so that the read and write of the register generates an interlock signal. When the nwrite signal is low, the data is written bit by bit from epp to the si pin. When the nwrite signal is high, the data is read bit by bit from epp; when the ndatastb pin is high, q0~q7 The data changes with the change of d0~d7. When the ndatastb pin is low, the latch enable signal is valid, and the data of the d segment is latched into the q terminal, and the data of the q end is changed to realize the mcp2510. Simulation of the spi signal.
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