1 Main features of DaVinci technology
The DaVinci platform is a typical embedded multi-processing (ARM, DSP, VICP, video front-end and back-end) environment based on shared storage. The key technology supported is the implementation of multi-channel switching center resources on-chip (Switch Central Resources) , SCR). Based on on-chip SCR, the DaVinci platform forms a typical C/S architecture between on-chip multiprocessors: a powerful DSP can serve as a real-time computing service for the server; an ARM9 with JAVA processing capability , hard disk audio and video I / O and other user interfaces. TI's Da Vinci platform has designed a system framework specifically for audio and video codec (Codec) multimedia applications, providing a rich system program interface SPI, API API and thousands of video, image, voice and audio. Streaming algorithm component. They and the operating system, middleware constitutes a large part of an application system, the application system development team only need to package them into a running package, you can get high availability and high reliability products.
The biggest feature of the DaVinci platform is the SOC chip based on DSP and ARM, and related software related to it, as shown in Figure 1.
For the DaVinci platform, the hardware supports strong dual-core architecture, DPS/BIOS is used to support the operation of audio/video algorithms on the DSP side, and MontaVistaLinux (MV) is used to support the management of peripherals on the ARM side. For data intersection between ARM and DSP, it is managed by Codec Engine and Codec Server. The advanced nature of the DaVinci platform is undoubtedly the best choice for high-end audio/video systems.
2 Introduction to TMS320DM365
TI's TMS320DM365 is a high-performance chip for multimedia technology applications. The functional block diagram of TM320DM365 is shown in Figure 2.
The TMS320DM365 integrates the ARM926EJ-SH264 coprocessor (HDVICP) and the MPEG4/JPEG coprocessor (MJCP) to provide H.264 codec in 1080p format and 10 frames/s, and 1080p and 24 frames. The /s speed provides MPEG4 codec and H.264 or MPEG4 codec in 720p and 30 frames/s. Storage aspect expansion memory interface EMIFs include a 16-bit 256 M address space DDR2 and mDDR, and a 16/8-bit AEMIF. The expandable types are 8/16-bit NAND Flash, 16Mb NOR Flash, SRAM, 16-bit. OneNAND and so on. Other peripheral expansion controllers also include 16-bit HPI (Host-Port Interface), 2 MMC (MulTImedia Card)/SD (Secure Digital)/SDIO interfaces, 1 16-bit WDT (Watch DogTImer), and 5 SPI (Serial) Each of the Port Interface interfaces has two chip selects, one master/slave I2C (Inter-Integrated Circuit) bus controller, and one support 2.0 USB OTG interface controller.
The TMS320DM365 integrated ARM926EJ-S processor includes 32 kBRAM, 16 kB ROM (for ARMbootloader in non-AEMIF boot mode), 16 kB instruction cache, 8 kB data cache, CP15 and MMU. The CP15 is used to configure and control the instructions, data cache, MMU and other ARM subsystems. MMU uses a unified TLB to cache information stored in page tables and provides virtual memory for operating systems such as Linux, Windows CE, ultron, and ThreadX. The processor's write buffer data capacity is up to 17 kB, which greatly improves the performance of the core.
The Video Processing Subsystem (VPSS) in the TMS320DM365 consists of two interfaces, a video capture front (VPFE) input interface for video capture and a video back end (VPBE) output interface for image display. Figure 3 is a block diagram of the video processing subsystem system.
The VPFE module is mainly used to capture video signals, and can also input existing video signals directly from the front end. The VPFE input interface consists of a CCD controller (CCDC), a pre-processor, a column module, an auto exposure/white balance/focus module (H3A) and registers. The CCDC can be connected to a video decoder, CMOS sensor or charge coupled device; the preprocessor is a real-time image processor that converts raw images from CMOS or CCD from RGB to YUV422; columnar and H3A modules are based on Hardware operation of raw image information.
The VPBE output interface consists of an OSD engine and a video encoder. The OSD engine can display two separate video windows or two separate OSD windows, and can also be displayed in the form of 2 video windows, 1 OSD window, and a property window. The OSD is used to superimpose volume, icon, etc. bitmap or image information on a video image. The video encoding module provides digital output and analog output. The digital output supports 24bit RGB888 format, 8/16bit BT.656 and CCIT.601 output with independent horizontal and vertical synchronization functions; the analog output supports 4 10bit DACs, all working at 54 MHz, supporting composite NTSC/PAL, S terminal and Component video.
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