The 74HC138 is a high speed CMOS device with a 74HC138 pin compatible low power Schottky TTL (LSTTL) family. The 74HC138 decoder accepts 3-bit binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive low active outputs (Y0 to Y7).
The 74HC138 features three enable inputs: two low active (E1 and E2) and one active high (E3). The 74HC138 will keep all outputs high unless E1 and E2 are set low and E3 is set high.
With this composite enable feature, only four 74HC138 chips and one inverter are needed to easily parallelize and combine into a 1-32 (5-wire to 32-wire) decoder. If a low active enable input is selected as the data input and the remaining enable inputs are used as the strobe, the 74HC138 can also function as an 8-output multiplexer. The unused enable inputs must remain bound. In each of the appropriate high effective or low effective states.
The 74HC138 is identical to the 74HC238 logic, except that the 74HC138 is an inverting output.
74HC138 function
CD74HC138, CD74HC238 and CD74HCT138, CD74HCT238 are high speed silicon gate CMOS decoders for memory address decoding or data routing applications. 74HC138 The principle of operation is high-performance memory decoding or data transmission system requiring short transmission delay time. In high-performance memory systems, the efficiency of the decoding system can be improved by using such a decoder. When the fast enabling circuit is used in the high speed memory, the delay time of the decoder and the enabling time of the memory are usually smaller than the typical access time of the memory, which is to say that the system is translated by Schottky clamp. The effective system delay caused by the encoder is negligible. The HC138 decodes a low level output from the 8 outputs in accordance with the 3-bit binary input code and the enable input conditions. Two active-low enable inputs and an active-high enable input reduce the external gate or inverter required for expansion, extending to a 24-wire decoder without external gates; expansion to 32 The line decoder only needs to connect an external inverter. In demodulator applications, the enable input can be used as a data input. 
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