The principle of the counter - do not understand it depends on ~~

Photocoupler

Introduction: The most used timing circuit in digital systems is the counter . The counter can be used not only to count clock pulses, but also to divide, time, generate beat pulses and pulse sequences, and perform digital operations. Let's introduce Xiaobian to the counter principle.

1. Counter principle - introduction

A counter is a device that can record the number of pulses and is the most commonly used logic component in digital circuits. In the digital system, the counter mainly counts the number of pulses to realize the functions of measurement, counting and control, and has a frequency dividing function. The counter consists of a basic counting unit and a number of control gates. The counting unit consists of a series of triggers with the function of storing information. Counters are widely used in digital systems, such as counting the address of an instruction in the controller of an electronic computer.

The counter is divided into a binary counter and a decimal counter according to the carry system; according to different calculation functions, it is divided into an addition counter, a subtraction counter and a reversible counter. Below we use the T flip-flop to form a binary addition and subtraction counter as an example to introduce the principle of the counter.

2. Counter principle - addition counter

Use a T flip-flop to form a binary addition counter, as shown in the following figure.

3-bit binary adder

As shown in the above figure, it is a 3-bit binary asynchronous adder consisting of three flip-flops triggered by three falling edges. The input signals of the J and K inputs of each flip-flop are all 1, and the output signal is mainly controlled by the pulse signal. The counter starts counting from the Q2 Q1 Q0 =000 state.

The operating waveforms of Q0, Q1, and Q2 are as shown in the following figure, that is, under the trigger of the falling of the counting input pulse CP, the output Q0 of the flip-flop FF0 is inverted. 0 becomes 1 or 1 becomes 0. Since CP1 is taken from Q0, the output Q1 of FF1 is flipped under the trigger of the falling edge of Q0. Similarly, since CP2=Q1, the output Q2 of FF2 is flipped under the trigger of the falling edge of Q1.

If the T' flip-flop triggered by the rising edge can also constitute an asynchronous binary addition counter, the carry pulse of each stage of the flip-flop should be changed to the Qˉ terminal output. The reason is very simple. When the Q terminal of the low-position flip-flop output changes from 1 to 0, the rising edge of Qˉ can be used as the trigger pulse of the high bit.

3. Counter principle - subtraction counter

If the T' flip-flops are connected by a binary subtraction rule, a binary subtraction counter can be obtained. According to the binary subtraction counting rule. If the low-order flip-flop is already 0, then after inputting a subtraction count pulse, it should be inverted to 1 and a borrow signal is sent to the high-order bit to make the high-order flip.

3-bit binary subtractor

The above figure is a 3-bit binary subtraction counter connected according to the above rules. In the figure, a D flip-flop connected by a rising action D flip-flop is used, in which D=Qˉ of all D flip-flops becomes a T' flip-flop. Its timing diagram is shown below.

The principle of the counter is introduced. Here are some counters recommended for everyone.