There are many alternatives to high-speed differential signaling. These differential technologies have the same characteristics, but performance, power consumption, and application scenarios are highly variable.
Differential technique
Industry standard
Maximum data rate
VOD output amplitude
Power consumption
LVDS
TIA/EIA-644
3.125Gbps
±350mV low
LVPECL
no
10+Gbps
±800mV
Medium to high
CML
no
10+Gbps
±800mV
in
M-LVDS
TIA/EIA-899
250Mbps
±550mV
low
B-LVDS
no
800Mbps
550mV
low
LVDS and M-LVDS techniques are defined in the international standards ANSI/TIA/EIA-644A and ANSI/TIA/EIA-899. Current-Mode Logic current mode logic and Low-Voltage Positive-Emitter-Coupled Logic low-voltage positive-emission-stage coupling logic technology are widely used in the industry. Due to the lack of corresponding industry standards, the implementation forms and interfaces of different manufacturers are quite different. AC coupling is used to resolve threshold differences and compatibility issues.
A typical LVDS driver receive pair is shown in Figure 1, with a 3.5mA current source on the driver side. Due to the high input impedance of the receiver, most of the effective current will flow through the 100Ω termination resistor, creating a 350mV drop across the input. The threshold voltage at the receiving end is generally not more than 100mV, and the common mode voltage can maintain such excitation between 0 and 2.4V, which can provide good noise margin and common mode drift tolerance at the driving end and the receiving end. When the direction of the current changes, the amplitude does not change and the polarity is reversed, thereby generating logical "1" and "0". CML and LVPECL have a similar structure, differing in drive current strength and termination strategy.
Figure 2 is a simplified diagram of the differential signal. First, the current source drives the logic "1" and "0" in different directions, and remains open at all times; compared to single-ended signal technology, switching noise and EMI caused by frequent switching of transistors can be eliminated. Secondly, the differential two lines are adjacent to each other to provide important noise immunity. The two single-line absorption intermodulation or EMI noise is consistent. The receiver only responds to the difference of the two channels, and the “common mode†noise is eliminated. . In addition, the minimum EMI is generated because the currents carried by the two lines are equal in amplitude.
2LVDS low voltage differential signaling technologyLVDS is highly efficient, with an output amplitude of approximately 350mV, achieving data rates up to 3.125Gbps with less energy consumption; simple termination strategy, low power consumption and low noise performance make LVDS technology tens of Mbps to 3Gbps Wide range of applications.
To achieve higher data rates, you need to use CML or LVPECL. Both technologies provide data rates in excess of 10 Gbps through very fast and steep transition edges and output amplitudes approaching 800 mV, thus consuming more energy than LVDS.
3CML current mode logic technology
The high-speed point-to-point form of the CML interface provides data rates in excess of 10 Gbps. As shown in Figure 3, CML usually integrates the termination network on both the driver and receiver terminals, and uses a passive 50Ω pull-up resistor to connect to the power supply. Signal transmission through AC coupling technology requires DC balance data transmission.
4LVPECL low voltage positive emitter coupling logic technologyBoth LVPECL and PECL are branches of ECL technology in the 1960s, and ECL is typically powered between ground and -5.2V. Due to the need for a female track, ECL is difficult to be compatible with other logic until PECL is introduced as a sun rail technology. ECL, PECL, and LVPECL all require a 50Ω termination to the rail end, which is 2V lower than most of the anode rails. The ECL driver is a low impedance open emitter output, approximately 700 to 800 mV, which produces very fast and balanced transition edges. The advantages of LVPECL are steep and balanced transition edges, high drive capability; the disadvantage is high power consumption, sometimes requiring separate termination rails.
When choosing a high-speed interface technology, you should pay attention to the following factors:
â— Required bandwidth
â— Ability to drive cables, backplanes or long wires
â— Power budget
â— Network topology
â— Serial or parallel data transmission
â— Compatibility between industry standards
â— Special requirements for signal conditions
As the most commonly used differential signal interface, LVDS has the widest application due to its low power consumption, weak EMI and strong noise immunity. In addition, LVDS's common-mode input range is wide enough to easily interoperate with other differential signaling technologies. The latest generation of LVDS operates from DC to 3.125 Gbps, and the device can route signals through lossy cables and printed boards through pre-emphasis and equalization.
CML signals are generally used at rates greater than 3.125 Gbps. Communication standards such as PCIe, SATA, and HDMI use rules consistent with CML to specify specific signal details.
Between 2Gbps and 3.125Gbps, the choice of high-speed interface depends on factors such as required functionality, performance, and power consumption. For relatively short-range transmissions, CML has minimal jitter and LVDS has the lowest power consumption. For long-distance transmission, dielectric loss occupies the main factor, the first to make the data rate and quality transmission conditions the best, LVDS and CML can use pre-emphasis, de-emphasis, equalization and other processing techniques.
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