FPGA Learning Series: 13. Any divider design

design background:

Frequency division has always played a very important role in the design of fpga. When it comes to frequency division, I believe that many people have already thought of using a calculator to calculate the desired clock frequency, but the problem is that only the counter is used to divide the frequency. Frequency, can only achieve even frequency division, and if I need to divide the frequency of the three, five, seven, and so on odd-numbered frequency division, then what to do? Here, let me introduce an arbitrary integer frequency division can be achieved The method, this method is also the same use of the counter to calculate, when it is different from the even frequency division is an arbitrary integer frequency division using two counters to achieve.

 

Design principle :  

This design is mainly to design an adjustable frequency divider, I can set its parameters, you can adjust the output of the duty cycle, the meaning of the duty cycle is the number of high cycle. We are instructed to calculate high time and low time, which is actually controlled by two counters.

 

Design architecture diagram :

State transition diagram

By counting the two counters, one calculates the next state of the jump, and waits until the next counter counts up and returns to the first state, thereby completing the design of an arbitrary frequency divider.

 

Design code :

Design module

 

0   Module fenpinqi ( clk , rst_n , clk0 );

1   Input clk ;

2   Input rst_n ;

3  

4   Output   Reg clk0 ;

5  

6   Parameter HW =   7   ;       // One high 7

7   Parameter LW =   3   ; //The low level is 3 or 5M clock

8  

9   Localparam s0 =   1'b0 ;      // Define two states

10 localparam s1 =   1'b1 ;

11

12 reg state ;

13 reg   [ 2 : 0 ] count ;

14

15 always   @( posedge clk or   negedge rst_n)

16 if (! rst_n )

17 begin

18 state <=   1'b0 ;

19 count <=   3'b0 ;

20 clk0 <=   1'b0 ;

21 end

22 else

23 begin

24 case   ( state )

25 s0 : begin

26

27 if ( HW +   1   >   1 ) / / To determine whether the HW is 0

28 if ( count < HW - 1   )    // Counter counts high

29 begin

30 clk0 <=   1'b1 ;    // generates a high level

31 count <= count +   1'b1 ;

32 end

33 else

34 begin

35 count <=   1'b0 ;

36 state <=   1 ;

37 end

38 end

39 s1 : begin

40 if ( LW +   1   >   1 )    / / Determine if LWW is 0

41 if ( count < LW - 1 ) // Counter counts low

42 begin

43 clk0 <=   1'b0 ;      // generates a low level

44 count <= count +   1'b1 ;

45 end

46 else

47 begin

48 count <=   1'b0 ;

49 state <=   0 ;

50 end

51 end

52 default : state <=   0 ;

53 endcase

54 end

55   Endmodule  

 

Test module

0   `timescale   1ns / 1ps

1   Module fenpinqi_tb ();

2  

3   Reg clk ;

4   Reg rst_n ;

5  

6   wire clk0;         // Define the output as wire type

7  

8   Parameter HW =   5 ;

9   Parameter LW =   1 ;

10

11 initial   Begin

12 clk =   1'b1 ;

13 rst_n =   1'b0 ;

14

15 # 200.1 rst_n =   1'b1 ;

16 # 2000   $stop ;

17 end

18 always   # 10 clk =   ~ clk ;      // Generate 50M clock

19

20 fenpinqi #(. HW ( HW ),. LW ( LW ))     // instantiation, we can change the duty cycle here, and frequency

21 fenpinqi_dut (

22 . clk ( clk ),

23. Rst_n (rst_n),

24. Clk0 (clk0)

25 );

26 endmodule  

 

Simulation diagram :

     In the figure, we can see that the output of output clk0 is 7 high and 3 low by the number of rising edges , which is in line with our design.

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